1. Field of the Invention
The invention relates to a method for programming a routing layout design, and more particularly, to a method that utilizes a single via layer for programming a routing layout design through two metal layers with predetermined metal trace allocation.
2. Description of the Prior Art
In the past, electrical elements, such as capacitances and resistances, have been connected through a rigid circuit board. However, as the development of semiconductor technologies progresses, integrated circuits (ICs) are widely applied to electrical devices, which means the electrical elements and metal traces for connecting those electrical elements are fabricated in the same chip by the same semiconductor process. Recently, sub-micro and deep sub-micro processes have been adopted to effectively reduce line widths of the elements, so that each chip can comprise many more elements and more complex circuits. Generally, the above-mentioned metal traces are formed on the metal layers. As semiconductor process technology develops, the amount of the metal layers for positioning the metal traces also increases. For example, a 0.18 micro process implements six metal layers for positioning metal traces. Concerning a 0.13 micro process, eight metal layers are implemented. Therefore, the required amount of photomasks for defining metal traces routed on all the metal layers increases as the semiconductor process technology progresses. In other words, the cost of the photomasks will occupy a great proportion of the total fabrication cost of ICs.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a structure of a prior art IC 10. The IC 10 comprises a device layer 12, a contact layer 13, a plurality of metal layers 14a, 14b, 14c, and 14d, and a plurality of via layers 15a, 15b, and 15c. The device layer 12 comprises elements, such as NMOS and PMOS transistors, on a wafer. Generally speaking, a pre-metal dielectric layer (PMD layer) is formed on the device layer 12 to make the surface of the device layer 12 more planar in conventional processes. Then, the contact layer 13 is formed on the device layer 12, which contains a plurality of contact plugs for connecting the elements positioned on the device layer 12. For example, a contact plug may be used for contacting one of the gate, the source, and the drain of a NMOS transistor or a PMOS transistor of the device layer 12. This means the contact plugs serve as corresponding contacts of the elements on the device layer 12. After forming the contact layer 13, a plurality of photomasks are utilized to define routing patterns on the metal layers 14a, 14b, 14c, and 14d for forming metal traces. Besides, a plurality of photomasks can be used for defining vias on the via layer 15a for electrically connecting the metal traces on the metal layers 14a and 14b. Similarly, a plurality of photomasks may be used to form vias on the via layer 15b and the via layer 15c for electrically connecting the metal traces on the metal layers 14b and 14c and the metal layers 14c and 14d respectively. In addition, the metal layer 14d on the top is used for disposing global traces, such as clock traces and power traces. Therefore, for correctly executing a predetermined logic operation, the elements of the device layer 12 have to be connected through the metal layers 14a, 14b, 14c, and 14d and the via layers 15a, 15b, and 15c for establishing corresponding current routes so as to transfer signals correctly.
Please refer to FIG. 2. FIG. 2 is a schematic diagram of the metal layers 14b and 14c shown in FIG. 1. The metal layer 14b comprises a plurality of horizontal metal traces 16a and 16b, and the metal layer 14c comprises a plurality of vertical metal traces 17a, 17b, 17c, 17d, and 17e. If the contact C1 of the metal layer 14c has to be electrically connected to the contact C2 of the metal layer 14c, only the metal trace 17c is needed for connecting the contacts C1 and C2 because the two contacts C1 and C2 are located in a same vertical track. However, if the contact A1 of the metal layer 14c has to be electrically connected to the contact A2 of the metal layer 14c, and the contact B1 of the metal layer 14c has to be electrically connected to the contact B2 of the metal layer 14c, the metal layer 14b and the via layer 15b have to be utilized to assist in connecting these contacts because the contacts A1, A2, B1, and B2 are located in different vertical tracks.
Referring to FIG. 2, the diagonal regions 18a, 18b, 18c, and 18d represent the overlapping regions of the metal traces 16a and 16b and the metal traces 17a, 17b, 17d, and 17e. For example, the metal trace 17a overlaps the metal trace 16a at the diagonal region 18a, and the metal trace 16a is overlapped with the metal trace 17e at the diagonal region 18d. Therefore, a via may be positioned in the via layer 15b at the diagonal region 18a for electrically connecting the metal traces 16a and 17a, and another via may be positioned in the via layer 15b at the diagonal region 18d for electrically connecting the metal traces 16a and 17e. Consequently, the contacts A1 and A2 can be electrically connected with each other through the metal traces 16a, 17a, 17e, and the vias positioned at the diagonal regions 18a and 18d. In the same way, the contact B1 can be electrically connected to the contact B2 through the metal traces 17b, 16b, 17d, and the vias positioned in the via layer 15b at the diagonal regions 18b and 18c which are the overlapping regions of the metal traces 17b, 16b and the metal traces 17d, 16b respectively.
As in the above description, the prior art makes uses of three photomasks to define the metal traces 16a, 16b, 17a, 17b, 17c, 17d, and 17e of the metal layers 14b, 14c, and the vias positioned at the diagonal regions 18a, 18b, 18c, 18d such that the IC 10 can execute a predetermined logic operation. However, even when the function of the IC 10 is slightly changed, those originally defined photomasks also have to be changed according to the changed current route design of the IC 10. For example, the patterns on the photomasks for defining the metal traces of the metal layers 14b and 14c have to be redesigned, thus the photomasks have to be refabricated. Accordingly, if there are only a few differences between two ICs having a similar main function, two specific photomasks have to be individually fabricated for these two ICs in the prior art. Therefore, the total fabrication cost of the IC rises because of the increased cost of additional photomasks.